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Features
* Also known as SMCS332SpW * 3 identical bidirectional SpaceWire links allowing
- full duplex communication - transmit rate from 1.25 up to 200 Mbit/s in each direction Derived from the TSS901E-SMCS332 triple IEEE 1355 high speed controller - Known anomalies of the TSS901E chip corrected - Slightly different startup behavior COmmunication Memory Interface (COMI) - autonomous accesses to a communication memory HOst Control Interface (HOCI) - gives read/write accesses to the AT7911E configuration registers - gives read/write accesses to the SpaceWire channels Arbitration unit - Allows two AT7911E to share one Dual Port RAM without external arbitration Scalable databus width - 8/16/32 bit width available - allows flexible integration with any CPU type Allows Little endian and Big endian configuration Performance - At 3.3V: 100 Mbit/s full duplex communication in each direction - At 5V: 200 Mbit/s full duplex communication in each direction Operating range - Voltages * 3V to 3.6V * 4.5V to 5.5V - Temperature * - 55 to +125 C C Maximum Power consumption - At 3.6V with a 15MHz clock : 0.4 W - At 5.5V with a 25 MHz clock : 1.7 W Radiation Performance - Total dose tested successfully up to 50 Krad (Si) - No single event latchup below a LET of 80 MeV/mg/cm2 ESD better than 2000V Quality Grades : - QML-Q or V with SMD Package : 196 pins MQFPL Mass : 12grams
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* *
Triple SpaceWire links High Speed Controller AT7911E
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1. Description
The AT7911E provides an interface between three SpaceWire links according to the SpaceWire standard ECSS-E-50-12A specification and a data processing node consisting of a Control Processing Unit and a communication data memory. The AT7911E was designed by EADS Astrium in Germany under the name 'SMCS332SpW" for "Scalable Multi-channel Communication Subsystem for SpaceWire". It is manufactured using the SEU hardened cell library from Atmel MG2RT CMOS 0.5m radiation tolerant sea of gates technology. For any technical question relative to the functionality of the AT7911E please contact Atmel technical support at assp-applab.hotline@nto.atmel.com. This document shall be read in conjunction with EADS Astrium 'SMCS332SpW User Manual'. The complete user manual of the AT7911E also called SMCS332SpW is available at www.atmel.com. The AT7911E provides hardware supported execution of the major parts of the interprocessor communication protocol, particularly: * * * Transfer of data between two nodes of a multi-processor system with minimal host CPU intervention Execution of simple commands to provide basic features for system control functions Provision of fault tolerant features.
Target applications are heterogeneous multi-processor systems supported by scalable interfaces including the little/big endian byte swapping. The AT7911E connects modules with different processors (e.g. TSC695F, AT697E and others). Any kind of network topology could be realized through the high speed point-to-point SpaceWire links (see the section `Applications'). It can also be used for modules without any communication features such as special image compression chips, some signal processors, application specific programmable logic or mass memory. The AT7911E may also be used in single board systems where standardised high speed interfaces are needed and systems containing "non-intelligent" modules such as A/D-converter or sensor interfaces which can be assembled with the AT7911E thanks to the "control by link" feature.
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AT7911E
Figure 1. AT7911E Block Diagram
CMADR Receive COMI CMDATA D/S RCV 1 D/S TRM 1 SpaceWire Protocol HADR H_CONTROL Transmit Channel1 HOCI HDATA HINTR CM_CONTROL
D/S RCV 2 D/S TRM 2 Channel2 PRCI
CPUR SES
D/S RCV 3 Channel3 D/S TRM 3 JTAG
TEST CLOCK RESET
The AT7911E is supported by VSPWorks from Wind River, a commercially available distributed real-time kernel. It is a multi-tasking as well as a multi-processor Operating System. The main goals are to enable programming at a higher level to configure and to perform communication and to administer the tasks on a board with multiple processes running in parallel. The VSPWorks kernel supports multiple processors and application specific chips, e.g. the TSC21020, the Sparc TSC695F, the AT697 etc.... Thus it is possible to run a heterogeneous multiprocessor system with a single Operating System without consideration of the hardware platform.
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2. Pin Configuration
Table 1. Pin assignment
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Name PLLOUT GND VCC CLK RESET* CLK10 HOSTBIGE TCK TMS TDI TRST* TDO VCC GND HSEL* HRD* HWR* HACK HINTR* VCC GND HADR0 HADR1 HADR2 HADR3 HADR4 HADR5 HADR6 HADR7 VCC GND BOOTLINK SCMSADR0 SMCSADR1 SMCSADR2 SMCSADR3 SMCSID0 SMCSID1 SMCSID2 SMCSID3 Pin Number 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Name VCC GND HDATA0 HDATA1 HDATA2 HDATA3 HDATA4 HDATA5 HDATA6 VCC GND HDATA7 HDATA8 HDATA9 HDATA10 HDATA11 VCC GND HDATA12 HDATA13 HDATA14 HDATA15 HDATA16 HDATA17 VCC GND HDATA18 HDATA19 HDATA20 HDATA21 HDATA22 HDATA23 VCC GND HDATA24 HDATA25 HDATA26 VCC GND HDATA27 Pin Number 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Name HDATA28 HDATA29 VCC GND HDATA30 HDATA31 CPUR* SES0* SES1* SES2* SES3* CAM COCI COCO CMCS0* CMCS1* VCC GND CMRD* CMWR* CMADR0 CMADR1 CMADR2 CMADR3 CMADR4 VCC GND CMADR5 CMADR6 CMADR7 CMADR8 CMADR9 CMADR10 CMADR11 VCC GND CMADR12 CMADR13 CMADR14 CMADR15 Pin Number 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 Name CMDATA0 CMDATA1 CMDATA2 VCC GND CMDATA3 CMDATA4 CMDATA5 VCC GND CMDATA6 CMDATA7 CMDATA8 VCC GND CMDATA9 CMDATA10 CMDATA11 CMDATA12 CMDATA13 CMDATA14 VCC GND CMDATA15 CMDATA16 CMDATA17 CMDATA18 CMDATA19 CMDATA20 VCC GND CMDATA21 CMDATA22 CMDATA23 VCC GND CMDATA24 CMDATA25 CMDATA26 VCC Pin Number 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 GND CMDATA27 CMDATA28 CMDATA29 CMDATA30 CMDATA31 GND GND VCC_3VOLT GND GND VCC GND GND NC LDI1 LSI1 LDO1 LSO1 LDI2 LSI2 NC VCC VCC VCC LDO2 LSO2 LDI3 LSI3 LDO3 LSO3 TIME_CODE_SYNC GND GND VCC GND Name
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3. Pin Description
Table 2. Pin description
5V 0.5V Signal Name(1)(3) HSEL* HRD* HWR* HADR(7:0) HDATA(31:0) HACK HINTR* SMCSADR(3:0 ) SMCSID(3:0) Type(2)(4) I I I I IO/Z O/Z O/Z I I Select host interface host interface read strobe host interface write strobe AT7911E register address lines. These address lines will be used to access (address) the AT7911E registers. AT7911E data host acknowledge. The AT7911E deasserts this output to add waitstates to an AT7911E access. After AT7911E is ready this output will be asserted. host interrupt request line Address. The binary value of these lines will be compared with the value of the ID lines. ID lines: offers possibility to use sixteen AT7911E within one HSEL* 0: host I/F Little Endian 1: host I/F Big Endian 0: control by host 1: control by link Communication memory select lines. These pins are asserted as chip selects for the corresponding banks of the communication memory. Communication memory read strobe. This pin is asserted when the AT7911E reads data from memory. Communication memory write strobe. This pin is asserted when the AT7911E writes to data memory. Communication memory address. The AT7911E outputs an address on these pins. Communication memory data. The AT7911E inputs and outputs data from and to com. memory on these pins. Communication interface 'occupied' input signal Communication interface 'occupied' output signal Communication interface arbitration master input signal 1: master 0: slave CPU Reset Signal (can be used as user defined flag) Specific External Signals (can be used as user defined flags) Link Data Input channel 1 Link Strobe Input channel 1 Link Data Output channel 1 12 6 25 3 3 1.5 1.5 50 50 3 1.5 50 6 3 25 3 3 3 1.5 1.5 1.5 50 50 50 Function max. output current [mA] 3.3V 0.3V max. output current [mA] load [pF]
HOSTBIGE
I
BOOTLINK
I
CMCS(1:0)*
O/Z
CMRD* CMWR* CMADR(15:0) CMDATA(31:0) COCI COCO CAM CPUR* SES(3:0)* LDI1 LSI1 LDO1
O/Z O/Z O/Z IOZ I O I O O I I O
6 6 6 3
3 3 3 1.5
25 25 25 25
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5V 0.5V Signal Name(1)(3) LSO1 LDI2 LSI2 LDO2 LSO2 LDI3 LSI3 LDO3 LSO3 TRST* TCK TMS TDI TDO Type(2)(4) O I I O O I I O O I I I I O Function max. output current [mA] Link Strobe Output channel 1 Link Data Input channel 2 Link Strobe Input channel 2 Link Data Output channel 2 Link Strobe Output channel 2 Link Data Input channel 3 Link Strobe Input channel 3 Link Data Output channel 3 Link Strobe Output channel 3 Test Reset. Resets the test state machine. Test Clock. Provides an asynchronous clock for JTAG boundary scan. Test Mode Select. Used to control the test state machine. Test Data Input. Provides serial data for the boundary scan logic. Test Data Output. Serial scan output of the boundary scan path. Reset. Sets the AT7911E to a known state. This input must be asserted (low) at power-up. The minimum width of RESET low is 5 cycles of CLK10 in parallel with CLK running. External clock input to AT7911E (max. 25 MHz). Must be derived from RAM access time. External clock input to AT7911E DS-links (application specific, nominal 10 MHz). Used to generate to transmission speed and link disconnect timeout. A falling edge on this signal sends (if enabled) the internal SpaceWire time code value over the links Output of internal PLL. Used to connect a network of external RC devices. This is not a PLL clock output. PLL Control signal - Configure PLL for 3.3V or 5V operation VCC_3VOLT I VCC = 5 Volt: connect this signal with GND VCC = 3.3 Volt: connect this signal with VCC VCC GND Power Supply Ground 3 12 12 12 12 12
3.3V 0.3V max. output current [mA] 6 25 load [pF]
6 6
25 25
6 6
25 25
1.5
50
RESET*
I
CLK
I
CLK10 TIME_CODE_SY NC PLLOUT
I
I O
Notes:
1. Groups of pins represent busses where the highest number is the MSB. 2. O = Output; I = Input; Z = High Impedance 3. (*) = active low signal 4. O/Z = if using a configuration with two AT7911Es these signals can directly be connected together (WIROR)
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AT7911E
4. Interfaces
The AT7911E provides an interface between three SpaceWire links according to the SpaceWire standard ECSS-E-50-12A specification and a data processing node consisting of a Central Processing Unit and a communication data memory. The AT7911E consists of the following blocks (See Figure 1): * Three bidirectional SpaceWire channels * Communication Memory Interface (COMI) * Host Control Interface (HOCI) * Protocol Command Interface (PRCI) * JTAG Test Interface
4.1
Three bidirectional SpaceWire channels,
Three bidirectional SpaceWire channels, all comprising the DS-link SpaceWire cell, receive and transmit sections (each including FIFOs) and a protocol processing unit (PPU). Each channel allows full duplex communication up to 200 Mbit/s in each direction. With protocol command execution a higher level of communication is supported. Link disconnect detection and parity check at character level are performed. A checksum generation for a check at packet level can be enabled. The transmit rate is selectable between 1.25 and 200 Mbit/s. The startup transmit rate is 10 Mbit/s. For special applications the data transmit rate can be programmed to values even below 10 Mbit/s; the lowest possible SpaceWire transmit rate is 1.25 Mbit/s (the next values are 2.5 and 5 Mbit/s).
4.1.1
PPU Functional Description Since the Protocol Processing Unit (PPU) determines a major part of the AT7911E functionality, the principal blocks of the PPU and their function are described here. The PPU unit functionality is provided for each SpaceWire channel of the AT7911E.
4.1.1.1
Protocol Execution Unit This unit serves as the main controller of the PPU block. It receives the character from the SpaceWire cell and interprets (in protocol mode) the four header data characters received after an EOP control character. If the address field matches the link channel address and the command field contains a valid command then forwarding of data into the receive FIFO is enabled. If the command field contains a "simple control command" then the execution request is forwarded to the command execution unit. The protocol execution unit also enables forwarding of header data characters to the acknowledge generator and provides an error signal in case of address mismatch, wrong commands or disabled safety critical "simple control commands". The protocol execution unit is disabled in "transparent" or "wormhole routing" operation mode.
4.1.1.2
Receive, Transmit, Acknowledge The transmit and receive FIFOs decouple the SpaceWire link related operations from the AT7911E related operations in all modes and such allows to keep the speed of the different units even when the source or sink of data is temporarily blocked.
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In the protocol mode an additional FIFO (acknowledge FIFO) is used to decouple sending of acknowledges from receiving new data when the transmit path is currently occupied by a running packet transmission. 4.1.1.3 Command Execution Unit This unit performs activating resp. deactivating of the CPU reset and the specific external signals and provides the capability to reset one or all links inside the AT7911E, all actions requested by the decoded commands from the protocol execution unit. The unit contains a register controlling the enable/disable state of safety critical commands which is set into the 'enable' state upon command request and which is reset after a safety critical command has been executed. The CPU reset and the specific external signals are forwarded to the Protocol Command Interface (PRCI).
4.2
Communication Memory Interface (COMI)
The COMI performs autonomous accesses to the communication memory of the module to store data received via the links or to read data to be transmitted via the links. The COMI consists of individual memory address generators for the receive and transmit direction of every SpaceWire link channel. The access to the memory is controlled via an arbitration unit providing a fair arbitration scheme. Two AT7911E can share one DPRAM without external arbitration logic. The data bus width is scalable (8/16/32 bit) to allow flexible integration with any CPU type. Operation in little or big endian mode is configurable through internal registers. The COMI address bus is 16 bit wide allowing direct access of up to 64K words (32 bits) of the DPRAM. Two chip select signals are provided to allow splitting of the 64k address space in two memory banks.
4.3
Host Control Interface (HOCI)
The HOCI gives read and write access to the AT7911E configuration registers and to the SpaceWire channels for the controlling CPU. Viewed from the CPU, the interface behaves like a peripheral that generates acknowledges to synchronize the data transfers and which is located somewhere in the CPU's address space. Packets can be transmitted or received directly via the HOCI. In this case the Communication Memory (DPRAM) is not strictly needed. However, in this case the packet size should be limited to avoid frequent CPU interaction. The data bus width is scalable (8/16/32 bit) to allow flexible integration with any CPU type. The byte alignment can be configured for little or big endian mode through an external pin. Additionally, the HOCI contains the interrupt signalling capability of the AT7911E by providing an interrupt output, the interrupt status register and interrupt mask register to the local CPU. A special pin is provided to select between control of the AT7911E by HOCI or by link. If control by link is enabled, the host data bus functions as a 32-bit general purpose interface (GPIO).
4.4
Protocol Command Interface (PRCI)
The PRCI collects the decoded commands from all PPUs and forwards them to external circuitry via 5 special pins.
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4.5 JTAG Test Interface
It represents the boundary scan testing provisions specified by IEEE Standard 1149.1 of the Joint Testing Action Group (JTAG). The AT7911E test access port and on-chip circuitry is fully compliant with the IEEE 1149.1 specification. The test access port enables boundary scan testing of circuitry connected to the AT7911E I/O pins.
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5. Control Interface
The AT7911E can be configured/controled through two interfaces: * HOCI interface * Link control interface
5.1
HOCI interface
The HOst Control Interface is especialy designed for access to internal AT6911E registers by a local controller (Controller, FPGA etc.). The detailed description of this operation mode can be found in the section 5.4 of the 'SMCS332SpW User Manual'.
5.2
Link control interface
Link control is the feature of the AT7911E that allows the control of the AT7911E not only via HOCI but via one of the three links. This allows to use the AT7911E in systems without a local controller. Since the HOCI is no longer used in this operation mode, it is instead available as a set of general purpose I/O (GPIO) lines. The detailed description of this operation mode can be found in the section 5.4 of the 'SMCS332SpW User Manual'.
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AT7911E
6. Operating Modes
According to the different protocol formats expected for the operation of the AT7911E, two major operation modes are implemented into the AT7911E. For each link channel the operation modes are chosen individually by setting the respective configuration registers via the HOCI or via the link.
6.1
Simple Interprocessor Communication (SIC) Protocol Mode
This mode executes the simple interprocessor communication protocol as described in the chapter 13 of the 'SMCS332SpW User Manual'. The following capabilities of the protocol are implemented into the AT7911E: * Interpretation of the first 4 data characters as the header bytes of the protocol * Autonomous execution of the simple control commands as described in the above mentioned chapter * Autonomous acknowledgement of received packets if configured In transmit direction no interpretation of the data is performed. This means that for transmit packets, the four header bytes must be generated by the host CPU and must be available as the first data read from the communication memory. EOP control characters are automatically inserted by the AT7911E when one configured transfer from the communication memory has finished.
6.2
Transparent Mode (default after reset)
This mode allows complete transparent data transfer between two nodes without performing any interpretation of the databytes and without generating any acknowledges. It is completely up to the host CPU to interpret the received data and to generate acknowledges if required. The AT7911E accepts EOP and EEP control tokens as packet delimiters and generates autonomously EOP or no EOP (as configured) marker after each end of a transmission packet. The transparent mode includes as a special submode: Wormhole routing.
6.2.1
Wormhole routing This mode allows hardware routing of packets by the AT7911E. It is a submode of the transparent mode. The AT7911E introduces a wormhole routing function similar to the routing implemented in the SpaceWire router. Each of the three links and the AT7911E itself can be assigned an eight bit address. When routing is enabled in the AT7911E, the first byte of a packet will be interpreted as the address destination byte, analysed and removed from the packet (header deletion). If this address matches one of the two other link addresses or the AT7911E address assigned previously, the packet will be automatically forwarded to this link or the FIFO of the AT7911E. If the header byte does not match a link address, the packet will be written to the internal FIFO as well and an error interrupt (maskable) will be raised.
7. Fault Tolerance
The SpaceWire standard specifies low level checks as link disconnect, credit value, sequence and parity at token level. The AT7911E provides, through the Protocol Processing Unit, features
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to reset a link or all links inside the AT7911E, to reset the local CPU or to send special signals to the CPU commanded via the links. Additionally it is possible to enable a checksum coder/decoder to have fault detection capabilities at packet level.
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AT7911E
8. Typical Applications
The AT7911E can be used for single board systems where standardised high speed interfaces are needed. Even "non-intelligent" modules such as A/D-converter or sensor interfaces can be assembled with the AT7911E because of the "control by link" feature. The complete control of the AT7911E can be done via link from a central controller-node. The AT7911E is a very high speed, scalable link-interface chip with fault tolerance features. The initial exploitation is for use in multi-processor systems where the standardization or the high speed of the links is an important issue and where reliability is a requirement. Further application examples are heterogeneous systems or modules without any communication features as special image compression chips, certain signal processors, application specific programmable logic or mass memory. The Figure below shows the AT7911E (also called SMCS332SpW) embedded in a typical module environment: Figure 8-1.
SMCS332SpW
HOSTBIGE BOOTLINK RESET CLK CLK10 HINTR HSEL HRD HWR HACK HDATA HADR 4 SPACEWIRE LINK 1 4 SPACEWIRE LINK 2 4 SPACEWIRE LINK 3 CPUR SES 4 SMCSADR SMCSID 8 4 4 ID 32
Typical Application
Processor
INTERRUPT IN CHIP SELECTS READ WRITE WAIT/ACK DATA ADDRESS
TIME_CODE_SYNC
CMCS0 CMCS1 CMRD CMWR CMDATA CMADR VCC CAM 32 16
SELECT A SELECT A OE A OE AA WE WE A A DATA DATA A ADDR A ADDR A
SELECT B SELECT B OE B OE B WE B DATAB WE B DATA B ADDR B
5 JTAG
COCO COCI GND PLLOUT
ADDR B Dual Port Communication Dual Port Memory Communication Memory
BANK 0 BANK 1
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8.1
AT7911E connected with the TSS901E (or SMCS332)
The new ECSS-E-50-12A SpaceWire standard, used by the AT7911E and the IEEE-1355 standard used by the old TSS901E are compatible, however the TSS901E has a slightly different startup behavior, the TSS901E must be started first on a link connecting with the AT7911E.
8.2
AT7911E differences with the TSS901E (or SMCS332)
A few differences between the AT7911E and the TSS901E exist in the registers and in the pinout. These differences are detailed in the section 14 of the `SMCS332SpW User Manual".
8.3
Handling empty packets
An anomaly due to the SpaceWire codec implemented in the AT7911E affect the behavior of the AT7911E when receiving empty packets. The description of this anomaly and the possible workaround are given in the section 12 of the `SMCS332SpW User Manual".
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9. PLL Filter
The AT7911E embeds a PLL to generate its internal clock reference. The PLLOUT pin of the PLL is the output of the AT7911E that allows connection of the external filter of the PLL. The following figure presents the connection of the PLL filter. Figure 9-1. PLL filter
AT7911E
Table 9-1.
PLL filter recommended components
VCC = +5V 0.5V VCC = +3.3V 0.3V
R1 C1 C2
1,8 k 5%, 1/4W 33pF, 5% 820pF, 5%
R1 C1 C2
2,0 k 5%, 1/4W 33pF, 5% 760pF, 5%
10. Power Supply
To achieve its fast cycle time, the AT7911E is designed with high speed drivers on output pins. Large peak currents may pass through a circuit board's ground and power lines, especially when many output drivers are simultaneously charging or discharging their load capacitances. These transient currents can cause disturbances on the power and ground lines. To minimize these effects, the AT7911E provides separate supply pins for its internal logic and for its external drivers. All GND pins should have a low impedance path to ground. A ground plane is required in AT7911E systems to reduce this impedance, minimizing noise. The VCC pins should be bypassed to the ground plane using approximately 10 high-frequency capacitors (0.1 F ceramic). Keep each capacitor's lead and trace length to the pins as short as possible. This low inductive path provides the AT7911E with the peak currents required when its output drivers switch. The capacitors' ground leads should also be short and connect directly to the ground plane. This provides a low impedance return path for the load capacitance of the AT7911E output drivers. The following pins must have a capacitor: 20, 78, 129, and 155. The remaining capacitors should be distributed equally around the AT7911E.
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11. Electrical Characteristics
11.1 Absolute Maximum Ratings
Table 11-1. Absolute Maximum Ratings
Parameter Supply Voltage I/O Voltage Operating Temperature Range (Ambient) Junction Temperature Storage Temperature Range Thermal resistance: junction to case TA TJ Tstg RThJC Symbol VCC Value -0.5 to +7 -0.5 to VCC + 0.5 -55 to +125 TJ < TA +20 -65 to +150 4 Unit V V C C C C/W
Stresses above those listed may cause permanent damage to the device.
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11.2 DC Electrical Characteristics
The AT7911E can work with VCC = + 5 V 0.5 V and VCC = + 3.3V 0.3V. Although specified for TTL outputs, all AT7911E outputs are CMOS compatible and will drive to VCC and GND assuming no DC loads. Table 11-2. 5V operating range DC Characteristics.
Parameter Operating Voltage Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Output LOW Voltage Output Short circuit current Symbol VCC VIH VIL VOH VOL IOS 2.4 0.4 90(1) 180(2) 270(3) Min. 4.5 2.2 0.8 Max. 5.5 Unit V V V V V mA mA mA IOL = 3, 6, 12mA / VCC = VCC(min) IOH = 3, 6, 12mA / VCC = VCC(min) VOUT = VCC VOUT = GND Conditions
Notes:
1. Applicable for HDATA[31:0], HACK, HINTR*, CMDATA[31:0], COCI, CPUR*, SES[3:0]* and TDO pins 2. Applicable for CMCS[1:0]*, CMRD*, CMWR* and CMADR[31:0] pins 3. Applicable for LDO1, LSO1, LDO2, LSO2, LDO3 and LSO3 pins
Table 11-3.
3.3V operating range DC Characteristics.
Parameter Symbol VCC VIH VIL VOH VOL IOS 2.4 0.4 50
(1) (2)
Min. 3.0 2.0
Max. 3.6
Unit V V
Conditions
Operating Voltage Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Output LOW Voltage Output Short circuit current
0.8
V V V mA mA mA IOL = 1.5, 3, 6mA / VCC = VCC(min) IOH = 1, 2, 4mA / VCC = VCC(min) VOUT = VCC VOUT = GND
100
155(3)
Notes:
1. Applicable for HDATA[31:0], HACK, HINTR*, CMDATA[31:0], COCI, CPUR*, SES[3:0]* and TDO pins 2. Applicable for CMCS[1:0]*, CMRD*, CMWR* and CMADR[31:0] pins 3. Applicable for LDO1, LSO1, LDO2, LSO2, LDO3 and LSO3 pins
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11.3
Power consumption
Max. power consumption figures at Vcc = 5.5V; -55 CLK = 25 MHz are presented in the folC; lowing table. Table 11-4. 5V Power Consumption
Operation Mode not clocked AT7911E in RESET AT7911E in IDLE Maximum
(1)
Power consumption [mA] 8 75 115 310
1.
IDLE means clk = 25 MHz, all three links started and running at 10Mbit/s, no activity on HOCI and COMI
Max. power consumption figures at Vcc = 3.6V; -55 CLK = 15 MHz are presented in the folC; lowing table. Table 11-5. 3.3V Power Consumption
Operation Mode not clocked AT7911E in RESET AT7911E in IDLE Maximum
(1)
Power consumption [mA] 4 24 38 100
1.
IDLE means clk = 15 MHz, all three links started and running at 10Mbit/s, no activity on HOCI and COMI
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11.4 AC Electrical Characteristics
The following table gives the worst case timings measured by Atmel on the 4.5V to 5.5V operating range Table 11-6. 5V operating range timings.
Parameter Propagation delay CLK Low to HACK High Propagation delay CLK High to CMCS0* Low Propagation delay CLK High to CMADR0 High Propagation delay CLK10 High to LDO1 High Propagation delay CLK10 High to LDO2 High Propagation delay CLK10 High to LDO3 High Symbol Tp1 Tp2 Tp3 Tp4 Tp5 Tp6 Min. Max. 29 18 17 30 32 36 Unit ns ns ns ns ns ns
The following table gives the worst case timings measured by Atmel on the 3.0V to 3.6V operating range Table 11-7. 3.3V operating range timings
Parameter Propagation delay CLK Low to HACK High Propagation delay CLK High to CMCS0* Low Propagation delay CLK High to CMADR0 High Propagation delay CLK10 High to LDO1 High Propagation delay CLK10 High to LDO2 High Propagation delay CLK10 High to LDO3 High Symbol Tp1 Tp2 Tp3 Tp4 Tp5 Tp6 Min. Max. 47 30 28 51 54 61 Unit ns ns ns ns ns ns
For guaranteed timings on the two operating voltage ranges, refer to the section 9 of the `SMCS332SpW User Manual'
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12. Ordering Information
Part-number AT7911EFA-E 5962-08A0101QXC 5962-08A0101VXC Temperature Range 25 C -55 to +125 C C -55 to +125 C C Package MQFPL196 MQFPL196 MQFPL196 Quality Flow Engineering sample Mil Level B (*) Space Level B (*)
(*) according to Atmel Quality flow document 4288, see Atmel web site.
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AT7911E
7737B-AERO-05/08
AT7911E
13. Package Drawings
196 pins Ceramic Quad Flat Pack (MQFP_L 196)
14. Document Revision History
14.1 7737B
1. Ordering information updated.
21
7737B-AERO-05/08
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7737B-AERO-05/08

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